Reliability test background ——

SiC power devices have a huge market in the field of efficient power conversion due to their material characteristics of high voltage, high frequency, high temperature and high power density. Among them, the development of SiC MOSFET attracts the most attention and can be widely used in power supply, photovoltaic, new energy vehicles and other fields.

For MOSFET devices, gate oxide reliability level is an important part of evaluating device reliability. Therefore, in order to replace the application of Si and meet the reliability requirements of industrial level and vehicle specification level, it is necessary to explore the reliability of SiC power device gate oxygen. Compared with Si material, SiC material has a larger band gap, so the properties of gate oxide interface of the two materials are different, and the failure mechanism and detection method are also different.

TDDB(time-dependent dielectric breakdown)As an experimental method to evaluate the reliability of gate oxygen, it can detect& To evaluate the quality of MOSFET gate oxide, at the same time, based on the experimental data, the service life prediction model of gate oxide and the screening model of gate oxide defective products can be established, which can meet the reliability requirements of devices.

SiC MOSFETFailure mechanism of gate oxide

　 For SiC power devices that meet high-voltage applications on the market today, the gate oxide thickness is generally greater than 5nm, so there is no so-called soft breakdown phenomenon when they fail, which is hard breakdown.

Among them, the failure mechanism of hard breakdown can be divided into internal failure(intrinsic failure)And extrinsic failure(extrinsic failure)。

The internal failure is caused by inherent defects, that is, there are no external defects. The quality level of gate oxide depends on the material itself (SiC/SiO2 interface); External failure is caused by non intrinsic defects, which can be understood as failure caused by micro defects or defects at the SiC/SiO2 interface or inside SiO2.

It has been debated whether the early failure of devices is internal or external.

There are some guesses about the mechanism of internal failure:

1) The early failure is caused by the inherent failure of gate oxide, which is due to the large Fowler Nordheim tunneling current at the SiC/SiO2 interface.

For the same electric field, Fowler Nordheim tunneling current in SiC MOSFET is much higher than that in Si MOSFET, because the conduction band offset between SiC and SiO2 is less than that between Si and SiO2.

As shown in the figure, in the Si-SiO2 interface, the conduction band offset is 3.2 eV, while that of 4H SiC is only 2.7 eV. The difference of 0.5eV in offset between the two makes the Fowler Nordheim tunneling current at 4H SiC/SiO2 interface 1.5 times larger than that at Si/SiO2 interface under the same electric field.

However, this can be ignored for devices with gate oxide thickness in the range of tens of nanometers. For SiC MOSFETs, Eox< The gate tunneling current is negligible at 3-5 MV/cm. Therefore, this conjecture is untenable.

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